As digital semiconductor Integrated Circuit (IC) geometries become smaller and signal speeds become faster, fault testing becomes more challenging. Various fault conditions such as marginal contacts, marginal vias, and marginal interconnects can cause signal delay faults.
Automatic Test Equipment (ATE) is used to generate test signals to exercise the digital IC and the resulting IC generated signals may be analyzed by the ATE and/or another external controller. An interface board, sometimes referred to as a Device Under Test (DUT) interface, is generally needed to adapt the ATE generated test signals to a particular IC. The ATE generated test signals generally include a clock signal and test vectors or patterns which are data streams tailored to test specific IC functions and/or signal paths, referred to generally as Automatic Test Pattern Generation (ATPG).
While delay fault testing is easiest achieved and therefore predominantly preformed at the wafer level, before the semiconductor wafer is separated for individual IC packaging, certain faults may occur after the IC is packaged. For example, the process of separating the semiconductor wafer and packaging the individual circuits can itself cause failures. Device level testing is sometimes performed where applications require; however, such testing even more complex and costly DUT boards than wafer level testing.
One type of fault testing is referred to as “stuck at” fault testing in which a signal line gets “stuck” at a particular voltage level. Testing for this type of fault is relatively simple and is achieved by measuring the voltage at various circuit nodes. Stuck at fault testing requires little to no timing information and is not particularly demanding on the ATE. However, stuck at fault testing may not be sufficient for certain critical applications. Another type of fault testing referred to as “at-speed” testing utilizes a clock signal having a frequency on the order of the operating frequency of the IC and is based on a transition and/or delay fault model. With at-speed testing, a test pattern is launched and the device response is captured at the operating speed.
At-speed delay fault testing may utilize a clock signal including a launch pulse and a capture pulse that have a close and precise timing relationship, such as a spacing on the order of 100 nanoseconds. One technique for generating such a launch/capture clock signal is with the use of a potentiometer in the ATE or the DUT interface board, with which the edge spacing is measured and the potentiometer adjusted to thereby adjust the edge spacing as desired. However, there are difficulties in measuring such close edge spacing without adversely impacting the clock signal itself. If the launch to capture pulse timing cannot be measured or measured accurately, then the potentiometer may be just adjusted until the DUT consistently passes a test, resulting in the test being run without accurate timing information.